In a liquid crystal display, an electric field is applied to a liquid crystal held between opposed substrates, for carrying out display. A liquid crystal display has a lighter weight, smaller power consumption and greater portability than those of a CRT. In particular, an active matrix liquid crystal display (AMLCD), in which a switching element such as a thin film transistor (TFT) is provided on a substrate to control an electric field to be applied to a liquid crystal, is very excellent in quality of display and has recently been applied to wide uses.
Referring to FIGS. 1 and 2, the active matrix liquid crystal display (AMLCD) will be described. FIG. 1 shows an example of circuit configuration in the AMLCD, which is referred to a so-called “Cs on Gate” AMLCD. The reference numeral 101 denotes a gate line for supplying a scanning signal, the reference numeral 102 denotes a source line for supplying a voltage signal, the reference numeral 103 denotes a thin film transistor (TFT) which is a switching element for applying a voltage to a liquid crystal, the reference numeral 104 denotes a liquid crystal for switching transmission/non-transmission of light which is represented as a capacitance on an equivalent circuit, the reference numeral 105 denotes a storage capacitance provided electrically in parallel with the liquid crystal 104 and serving to reduce the influence of a parasitic capacitance of a TFT, the reference numeral 106 denotes a connecting portion for connecting an electrode on either side of the liquid crystal 104 to a common voltage, the reference numeral 107 denotes a gate terminal for connecting an external circuit on the gate side to the gate line 101 through a TCP or the like, the reference numeral 108 denotes a source terminal for connecting an external circuit on the source side to the source line 102 through the TCP or the like, the reference numeral 111 denotes a line connected to the gate lines 101, the reference numeral 112 denotes a line connected to the source lines 102, and the reference numeral 113 denotes a connection for connecting the line 111 to the line 112. The reference numeral 114 denotes a repair line to be used when the source line is open. Although not shown in FIG. 1, a component which may be a TFT or an element of high resistance having linear or non linear characteristics may be provided between the gate terminal 107 and line 111 and between the source terminal 108 and line 112 to electrically isolate the gate terminal 107 and source terminal 108 during signal application and to electrically connect the gate terminal 107 and source terminal 108 when static electricity of high voltage invades. In many cases, a TFT array is formed with such a configuration as shown in FIG. 1 as described above. After combined with a counter substrate on which a color filter is provided, a liquid crystal is injected therebetween and the outside of a region 115 shown in a dotted line in the drawing is generally cut out to form a liquid crystal display.
While the repair line 114, for example, formed of the same material of the gate line to be a substitute of the source line is shown in FIG. 1, it does not need to be formed depending on circumstances.
FIG. 2(a) is a partially enlarged plan view showing the TFT array of the AMLCD in FIG. 1 and FIG. 2(b) is a sectional view taken along the line X—X in FIG. 2(a). Since a terminal portion 303 is provided on the outside of the region of FIG. 2(a), it is shown in only FIG. 2(b).
In FIG. 2, the reference numeral 211 denotes an insulative substrate, the reference numeral 212 denotes a gate line formed of a conductive film, the reference numeral 221 denotes a storage capacitance electrode, the reference numeral 224 denotes a source line, the reference numeral 225 denotes a drain electrode, and the reference numeral 214 denotes a pixel electrode formed of a transparent conductive layer. In the Cs on Gate AMLCD, the gate line 212 also serves as the storage capacitance electrode 221 and the storage capacitance 105 is formed between the gate line 212 and the pixel electrode 214.
A process for manufacturing the TFT array in FIG. 2 will be described with reference to FIGS. 3, 4 and 5.
First of all, a first conductive film is formed on the first insulative substrate 211. The first conductive film is formed of metal such as Cr, Al, Ti, Ta, Au, Ag, W, Mo, Mo—W or Cu, an alloy including either of or some of these metals as essential components, or a laminated layer of these metals and/or alloys, by a method such as sputtering, evaporation, CVD or printing. Subsequently, the gate line 212 and the storage capacitance electrode 221 are formed by photolithography and succeeding etching (FIG. 3(a)).
Then, an insulating film 216 comprising Si3N4 is formed by a plasma CVD method, another suitable CVD method, sputtering, evaporation, coating or the like, and furthermore, an a−Si:H film 217 (a hydroxide amorphous silicon film) and an n+Si:H film 218 doped with an impurity such as phosphorus are continuously formed by a plasma CVD method, another suitable CVD method or sputtering.
Next, a second conductor layer 220 is formed of metal such as Cr, Al, Ti, Ta, Au, Ag, W, Mo, Mo—W or Cu, an alloy including either of or some of these metals as essential components or a laminated layer of these metals and/or alloys (FIG. 3(b)).
Subsequently, the whole surface is first coated with a photosensitive organic resin which can be used as a photoresist. Then, a photoresist pattern 219 is formed by exposure using a photomask (FIG. 3(c)). The shape of the photoresist pattern 219 will be described in detail.
First of all, at least a part of a portion to be a pixel electrode later is set to be a region (region C) in which the photoresist is not formed. Moreover, at least a portion to be a source electrode and a drain electrode later are set to be a region (region A) in which the photoresist has a great thickness. Moreover, a portion in which the second conductor layer 220 and the n+Si:H film 218 are removed by etching to leave the a−Si:H film 217, for example, a channel portion 226 of the TFT is set to be a region (region B) in which the photoresist has a small thickness.
Subsequently, the etching is carried out by using the photoresist pattern 219. First of all, the second conductor layer 220 is etched by wet or dry etching or the like. Then, the n+Si:H film 218 and the a−Si:H film 217 are etched. The conductor layer 220, the n+Si:H film 218 and the a−Si:H film 217 in the region C are removed (FIG. 4(a)).
Thereafter, ashing is carried out by using plasma capable of reducing the thickness of the photoresist, for example, an oxygen plasma, thereby scraping the photoresist to be removed from the region B (FIG. 4(b)). At this time, the thickness of the photoresist in the region A becomes smaller than an initial thickness, but the ashing is controlled to maintain such a thickness as to fully protect a portion which is not etched during etching at a subsequent step.
Subsequently, the second conductor layer 220 exposed by removing the photoresist in the region B is removed by wet or dry etching or the like.
Then, at least the n+Si:H film 218 in the region B is removed by the dry etching or the like and the photoresist is finally peeled to form a predetermined pattern (FIG. 4(c)).
Thereafter, a protective film 222 is formed by an insulating film comprising Si3N4 or SiO2, or their mixture and lamination. A photoresist pattern is provided by photolithography for forming a contact hole 233 in a gate terminal portion, a source terminal portion and a drain electrode portion, and subsequently, the contact hole 233 is formed by dry etching or wet etching using a CF4 based gas. After the etching is completed, the photoresist is removed (FIG. 5(a)).
Next, a transparent conductive layer comprising a transparent conductive film such as ITO, SnO2 or InZnO, a laminated layer thereof or a layer of mixture thereof is formed on the protective film 222 by a method such as sputtering, evaporation, coating, CVD, printing or a sol-gel method, and desirable patterns of the pixel electrode 214, an upper pad 215 and the like are formed by photolithography and succeeding wet or dry etching or the like, so that a TFT array is formed (FIG. 5(b)).
Furthermore, an orientation film is formed on the TFT array and is opposed to a counter substrate having at least an orientation film and a common electrode on its surface, and a liquid crystal is injected therebetween to form an active matrix liquid crystal display, although not shown in the figures. Through the above-mentioned steps, the TFT array and a liquid crystal display using the TFT array are formed.
In order to form the photoresist pattern 219 having the region A in which the photoresist has a great thickness, the region B in which the photoresist has a small thickness and the region C in which the photoresist is removed (the thickness is substantially zero) as shown in FIG. 3(c), a so-called halftone mask is used as a photomask.
The halftone mask is a photomask capable of carrying out intermediate exposure in addition to a binary process in which light illuminated from an exposing machine is transmitted or interrupted depending on the presence of a shielding film. The intermediate exposure can be obtained by alternately arranging a transmitting portion through which illuminated light is transmitted and a shielding portion through which illuminated light is not transmitted to thereby constitute a transmitting/shielding pattern and by sufficiently increasing the spatial frequency of the transmitting/shielding pattern than the pattern resolution of the exposing machine. Consequently, the transmitting/shielding pattern cannot be accurately exposed with the pattern resolution of the exposing machine, and the whole region of the photoresist below the transmitting/shielding pattern is exposed in an intermediate amount of exposure.
An actual halftone mask pattern is illustrated in FIGS. 6 and 7. A mask pattern SH1 in FIG. 6 has a region A1 for shielding the illuminated light of the exposing machine and a halftone region B1 corresponding to the region B of the photoresist pattern 219, and the halftone region B1 is defined by transmitting/shielding pattern having a plurality of fine rectangular transmitting portions. The fine transmitting/shielding pattern cannot be drawn with the pattern resolution of the exposing machine. For this reason, the whole halftone region B1 is exposed weakly.
A mask pattern SH2 in FIG. 7 has a region A2 for shielding the illuminated light of the exposing machine and a halftone region B2 corresponding to the region B of the photoresist pattern 219, and the halftone region B2 is defined by a stripe-shaped transmitting/shielding pattern. As a matter of course, the fine transmitting/shielding pattern cannot be drawn with the pattern resolution of the exposing machine. For this reason, the whole halftone region B2 is exposed weakly.
A photoresist pattern formed by using the halftone mask shown in FIG. 6 or 7 has such a thickness as shown in an explanatory view of FIG. 8. FIG. 8 shows the thickness of the photoresist in a shade of color, and a dark portion represents a region in which the photoresist has a great thickness and a light portion represents a region in which the photoresist has a small thickness. Moreover, FIG. 9 shows the result obtained by carrying out a simulation using LILE (TRADE NAME; manufactured by Seiko Instruments) for the amount of exposure in the TFT array surface in the case in which the exposure is performed by using the halftone mask in FIG. 6 or FIG. 7. The result indicates a relative value, wherein the amount of exposure without the halftone mask is set to 1. Moreover, the conditions of the simulation are as follows.
Simulation Condition:
Exposure wavelength=0.436 μm (g ray)
Numerical aperture (NA) of projection lens of stepper=0.1
Illumination system coherency (σ)=0.5
As is apparent from FIGS. 8 and 9, the thickness of the photoresist in the region B (halftone regions B1 or B2) is smaller than that of the photoresist in the region A. However, the thickness of the photoresist in the region B has a variation to show a poor uniformity.
Accordingly, the photoresist in the region B is partially dissipated due to a fluctuation in the amount of exposure during exposure. To the contrary, the thickness of the photoresist in the region B is left too thickly so that a time required for removing the photoresist is increased at the time of ashing or the photoresist removing defect is partially caused. Consequently, yield is deteriorated or tact is increased.
Moreover, in the case in which a plurality of halftone masks are used for one substrate to carry out the exposure, the amount of the exposure in the region B are varied. As a matter of course, the photoresist is partially dissipated, the time required for removing the photoresist is increased and the photoresist removing defect is partially caused. Consequently, the yield is deteriorated and the tact is increased.
For these reasons, the manufacturing cost of the TFT array is necessarily increased. Moreover, the defect of the shape of the TFT is caused by the nonuniformity of the thickness of the photoresist. In particular, a variation in the length of a TFT channel portion is increased so that a display characteristic is deteriorated.
The present invention has been made in consideration of the above-mentioned problems in the prior arts, and has an object to enhance the uniformity of the thickness of a photoresist in a halftone region and to implement high yield and low tact, and to suppress a variation in the channel length of a TFT to obtain display of high quality when forming the photoresist pattern by using a halftone mask.